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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. unless otherwise noted, this document contains production data. UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 UCC21220, UCC21220a 4-a, 6-a, 3.0-kv rms isolated dual-channel gate driver 1 1 features 1 ? narrow body soic-16 (d) package ? universal: dual low-side, dual high-side or half- bridge driver ? switching parameters: ? 28-ns typical propagation delay ? 10-ns minimum pulse width ? 5-ns maximum delay matching ? 5.5-ns maximum pulse-width distortion ? integrated deglitch filter ? common-mode transient immunity (cmti) greater than 100-v/ns ? 1.5-kv channel-to-channel functional isolation ? isolation barrier life > 40 years ? 4-a peak source, 6-a peak sink output ? ttl and cmos compatible inputs ? 3-v to 5.5-v input vcci range ? up to 18-v vdd output drive supply ? 5-v and 8-v vdd uvlo options ? i/os withstand ? 2-v for 200 ns ? rejects input pulses and noise transients shorter than 5-ns ? uvlo protection for all power supplies ? active pull down protection at outputs ? fast disable for power sequencing ? operating temp. range (t a ) ? 40 c to 125 c ? surge immunity up to 7800-v pk ? safety-related certifications (planned): ? 4242-v pk isolation per din v vde v 0884- 11:2017-01 and din en 61010-1 ? 3000-v rms isolation for 1 minute per ul 1577 ? csa certification per iec 60950-1, iec 62368- 1 and iec 61010-1 end equipment standards ? cqc certification per gb4943.1-2011 2 applications ? ac-to-dc and dc-to-dc power supplies ? server, telecom, it and industrial infrastructures ? motor drive and solar inverters ? hev and bev battery chargers ? industrial transportation ? uninterruptible power supply (ups) 3 description the UCC21220 and UCC21220a devices are isolated dual-channel gate driver with 4-a peak- source and 6-a peak-sink current. it is designed to drive power mosfet, igbt, and gan transistors with the best-in-class dynamic performance. the devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions without internal shoot-through due to the best-in-class delay matching performance. the input side is isolated from the two output drivers by a 3.0-kv rms isolation barrier, with a minimum of 100-v/ns common-mode transient immunity (cmti). protection features include: dis pin shuts down both outputs simultaneously when it is set high; ina/b pin rejects input transient shorter than 5-ns; both inputs and outputs can withstand ? 2-v spikes for 200-ns, all supplies have undervoltage lockout (uvlo), and active pull down protection clamps the output below 2.1-v when unpowered or floated. with these features, the device enables high efficiency, high power density, and robustness in a wide variety of power applications. device information (1) part number package uvlo UCC21220 soic (16) 8-v UCC21220a (advance information) soic (16) 5-v (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram productfolder 10 9 11 driver vddb outb vssb 12 13 nc nc uvlo demod mod 15 14 16 driver vdda outa vssa uvlo demod mod functional isolation isolation barrier input logic, disable, uvlo 2 1 3,8 4 7 5 6 gnd inb nc nc dis ina vcci copyright ? 2017, texas instruments incorporated support &community tools & software technical documents ordernow
2 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 6 7.5 power ratings ........................................................... 6 7.6 insulation specifications ............................................ 7 7.7 safety-related certifications ..................................... 8 7.8 safety-limiting values .............................................. 8 7.9 electrical characteristics ........................................... 9 7.10 switching characteristics ...................................... 10 7.11 thermal derating curves ...................................... 10 7.12 typical characteristics .......................................... 11 8 parameter measurement information ................ 15 8.1 minimum pulses ...................................................... 15 8.2 propagation delay and pulse width distortion ....... 15 8.3 rising and falling time ......................................... 15 8.4 input and disable response time .......................... 16 8.5 power-up uvlo delay to output ........................ 16 8.6 cmti testing ........................................................... 17 9 detailed description ............................................ 18 9.1 overview ................................................................. 18 9.2 functional block diagram ....................................... 18 9.3 feature description ................................................. 19 9.4 device functional modes ........................................ 22 10 application and implementation ........................ 23 10.1 application information .......................................... 23 10.2 typical application ................................................ 23 11 power supply recommendations ..................... 33 12 layout ................................................................... 34 12.1 layout guidelines ................................................. 34 12.2 layout example .................................................... 35 13 device and documentation support ................. 37 13.1 documentation support ....................................... 37 13.2 related links ........................................................ 37 13.3 receiving notification of documentation updates 37 13.4 community resources .......................................... 37 13.5 trademarks ........................................................... 37 13.6 electrostatic discharge caution ............................ 37 13.7 glossary ................................................................ 37 14 mechanical, packaging, and orderable information ........................................................... 37 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (may 2018) to revision c page ? added 5v vdd uvlo threshold and hysteresis graph in typical characteristics section .................................................. 11 changes from revision a (december 2017) to revision b page ? added UCC21220a advance information device. ................................................................................................................ 1 ? changed dti from 16 m to 17 m in insulation specifications table .................................................................................... 7 changes from original (november 2017) to revision a page ? changed data sheet status from advance information to production data ........................................................................... 1 ? changed maximum pulse-width distortion from " 5-ns " to " 5.5-ns " in features section ........................................................ 1 ? changed vdd uvlo from " -5-v for 100 ns " to " ? 2-v for 200 ns " in features section .......................................................... 1 ? clarified descriptions in pin functions table ........................................................................................................................... 4 ? separated figure titles and condition statements in typical characteristics section ............................................................ 11 ? added typical timing specifications to power-up uvlo delay to output section ............................................................. 16 ? added guideline to layout guidelines section ..................................................................................................................... 34
3 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 5 device comparison table device options uvlo recommended vdd supply min. package UCC21220d 8-v 9.2-v narrow body soic-16 UCC21220ad 5-v 6.0-v narrow body soic-16
4 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) p = power, g = ground, i = input, o = output 6 pin configuration and functions d package 16-pin soic top view pin functions pin i/o (1) description dis 5 i disables both driver outputs if asserted high, enables if set low or left open. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. bypass using a 1-nf low esr/esl capacitor close to dis pin when connecting to a c with distance. gnd 4 p primary-side ground reference. all signals in the primary side are referenced to this ground. ina 1 i input signal for a channel. ina input has a ttl/cmos compatible input threshold. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. inb 2 i input signal for b channel. inb input has a ttl/cmos compatible input threshold. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. nc 6 no internal connection. 7 12 13 outa 15 o output of driver a. connect to the gate of the a channel fet or igbt. outb 10 o output of driver b. connect to the gate of the b channel fet or igbt. vcci 3 p primary-side supply voltage. locally decoupled to gnd using a low esr/esl capacitor located as close to the device as possible. vcci 8 p this pin is internally shorted to pin 3. vdda 16 p secondary-side power for driver a. locally decoupled to vssa using a low esr/esl capacitor located as close to the device as possible. vddb 11 p secondary-side power for driver b. locally decoupled to vssb using a low esr/esl capacitor located as close to the device as possible. vssa 14 p ground for secondary-side driver a. ground reference for secondary side a channel. vssb 9 p ground for secondary-side driver b. ground reference for secondary side b channel. 1 ina 16 vdda 2 inb 15 outa 3 vcci 14 vssa 4 gnd 13 nc 5 dis 12 nc 6 nc 11 vddb 7 nc 10 outb 8 vcci 9 vssb not to scale
5 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) values are verified by characterization and are not production tested. (3) to maintain the recommended operating conditions for t j , see the thermal information . 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input bias pin supply voltage vcci to gnd ? 0.5 6 v driver bias supply vdda-vssa, vddb-vssb ? 0.5 20 v output signal voltage outa to vssa, outb to vssb ? 0.5 v vdda +0.5, v vddb +0.5 v outa to vssa, outb to vssb, transient for 200 ns (2) ? 2 v vdda +0.5, v vddb +0.5 v input signal voltage ina, inb, dis to gnd ? 0.5 v vcci +0.5 v ina, inb transient to gnd for 200ns (2) ? 2 v vcci +0.5 v junction temperature, t j (3) ? 40 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 4000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1500 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit vcci vcci input supply voltage 3 5.5 v vdda, vddb driver output bias supply UCC21220 ? 8v uvlo version 9.2 18 v UCC21220a ? 5v uvlo version 6.0 18 v t j junction temperature ? 40 130 c t a ambient temperature ? 40 125 c
6 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 7.4 thermal information thermal metric (1) UCC21220, UCC21220a unit d (soic) 16 pins r ja junction-to-ambient thermal resistance 68.5 c/w r jc(top) junction-to-case (top) thermal resistance 30.5 c/w r jb junction-to-board thermal resistance 22.8 c/w jt junction-to-top characterization parameter 17.1 c/w jb junction-to-board characterization parameter 22.5 c/w 7.5 power ratings value unit p d power dissipation vcci = 5.5 v, vdda/b = 12 v, ina/b = 3.3 v, 5.4 mhz 50% duty cycle square wave 1.0- nf load 1825 mw p di power dissipation by transmitter side 15 mw p da , p db power dissipation by each driver side 905 mw
7 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) this coupler is suitable for basic electrical insulation only within the maximum operating ratings. compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) apparent charge is electrical discharge caused by a partial discharge (pd). (5) all pins on each side of the barrier tied together creating a two-pin device. 7.6 insulation specifications parameter test conditions value unit clr external clearance (1) shortest pin-to-pin distance through air > 4 mm cpg external creepage (1) shortest pin-to-pin distance across the package surface > 4 mm dti distance through the insulation minimum internal gap (internal clearance) > 17 m cti comparative tracking index din en 60112 (vde 0303-11); iec 60112 > 600 v material group i overvoltage category per iec 60664-1 rated mains voltage 150 v rms i-iv rated mains voltage 300 v rms i-iii rated mains voltage 600 v rms i-ii din v vde v 0884-11:2017-01 (2) v iorm maximum repetitive peak isolation voltage ac voltage (bipolar) 990 v pk v iowm maximum working isolation voltage ac voltage (sine wave); time dependent dielectric breakdown (tddb) test; 700 v rms dc voltage 990 v dc v iotm maximum transient isolation voltage v test = v iotm , t = 60 s (qualification); v test = 1.2 v iotm , t = 1 s (100% production) 4242 v pk v iosm maximum surge isolation voltage (3) test method per iec 62368-1, 1.2/50 s waveform, v test = 1.3 v iosm = 7800 v pk (qualification) 6000 v pk q pd apparent charge (4) method a, after i/o safety test subgroup 2/3, v ini = v iotm , t ini = 60 s; v pd(m) = 1.2 v iorm , t m = 10 s < 5 pc method a, after environmental tests subgroup 1, v ini = v iotm , t ini = 60 s; v pd(m) = 1.2 v iorm , t m = 10 s < 5 method b1; at routine test (100% production) and preconditioning (type test) v ini = 1.2 v iotm ; t ini = 1 s; v pd(m) = 1.5 v iorm , t m = 1 s < 5 c io barrier capacitance, input to output (5) v io = 0.4 sin (2 ft), f =1 mhz 0.5 pf r io isolation resistance, input to output (5) v io = 500 v at t a = 25 c > 10 12 v io = 500 v at 100 c t a 125 c > 10 11 v io = 500 v at t s =150 c > 10 9 pollution degree 2 climatic category 40/125/21 ul 1577 v iso withstand isolation voltage v test = v iso = 3000 v rms , t = 60 s. (qualification), v test = 1.2 v iso = 3600 v rms , t = 1 s (100% production) 3000 v rms
8 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7.7 safety-related certifications vde csa ul cqc plan to certify according to din v vde v 0884-11:2017- 01 and din en 61010-1 (vde 0411-1):2011-07 plan to certify according to iec 60950- 1, iec 62368-1 and iec 61010-1 plan to certify under ul 1577 component recognition program plan to certify according to gb 4943.1-2011 (1) the maximum safety temperature, t s , has the same value as the maximum junction temperature, t j , specified for the device. the i s and p s parameters represent the safety current and safety power respectively. the maximum limits of i s and p s should not be exceeded. these limits vary with the ambient temperature, t a . the junction-to-air thermal resistance, r ja , in the thermal information table is that of a device installed on a high-k test board for leaded surface-mount packages. use these equations to calculate the value for each parameter: t j = t a + r ja p, where p is the power dissipated in the device. t j(max) = t s = t a + r ja p s , where t j(max) is the maximum allowed junction temperature. p s = i s v i , where v i is the maximum input voltage. 7.8 safety-limiting values safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. parameter test conditions side min typ max unit i s safety output supply current r ja = 68.5 o c/w, v vdda/b = 12 v, t j = 150 c, t a = 25 c see figure 1 driver a, driver b 75 ma p s safety supply power r ja = 68.5 o c/w, v vcci = 5.5 v, t j = 150 c, t a = 25 c see figure 2 input 15 mw driver a 905 driver b 905 total 1825 t s safety temperature (1) 150 c
9 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted). (2) parameters that has only typical values, are not production tested and guaranteed by design. 7.9 electrical characteristics v vcci = 3.3 v or 5.0 v, 0.1- f capacitor from vcci to gnd and 1uf capacitor from vdda/b to vssa/b, v vdda = v vddb = 12 v, 1- f capacitor from vdda and vddb to vssa and vssb, t a = ? 40 c to +125 c, unless otherwise noted (1) (2) . parameter test conditions min typ max unit supply currents i vcci vcci quiescent current v ina = 0 v, v inb = 0 v 1.5 2.0 ma i vdda , i vddb vdda and vddb quiescent current v ina = 0 v, v inb = 0 v 1.0 1.8 ma i vcci vcci operating current (f = 500 khz) current per channel 2.5 ma i vdda , i vddb vdda and vddb operating current (f = 500 khz) current per channel, c out = 100 pf, v vdda , v vddb = 12 v 2.5 ma vcc supply voltage undervoltage thresholds v vcci_on uvlo rising threshold 2.55 2.7 2.85 v v vcci_off uvlo falling threshold 2.35 2.5 2.65 v v vcci_hys uvlo threshold hysteresis 0.2 v UCC21220a vdd supply voltage undervoltage thresholds (5-v uvlo version) v vdda_on , v vddb_on uvlo rising threshold 5.0 5.5 5.9 v v vdda_off , v vddb_off uvlo falling threshold 4.7 5.2 5.6 v v vdda_hys , v vddb_hys uvlo threshold hysteresis 0.3 v UCC21220 vdd supply voltage undervoltage thresholds (8-v uvlo version) v vdda_on , v vddb_on uvlo rising threshold 8 8.5 9 v v vdda_off , v vddb_off uvlo falling threshold 7.5 8 8.5 v v vdda_hys , v vddb_hys uvlo threshold hysteresis 0.5 v ina, inb and disable v inah , v inbh , v dish input high threshold voltage 1.6 1.8 2 v v inal , v inbl , v disl input low threshold voltage 0.8 1 1.25 v v ina_hys , v inb_hys , v dis_hys input threshold hysteresis 0.8 v output i oa+ , i ob+ peak output source current c vdd = 10 f, c load = 0.18 f, f = 1 khz, bench measurement 4 a i oa- , i ob- peak output sink current c vdd = 10 f, c load = 0.18 f, f = 1 khz, bench measurement 6 a r oha , r ohb output resistance at high state i out = ? 10 ma, r oha , r ohb do not represent drive pull-up performance. see t rise in switching characteristics and output stage for more details. 5 r ola , r olb output resistance at low state i out = 10 ma 0.55 v oha , v ohb output voltage at high state v vdd = 12 v, i out = ? 10 ma 11.95 v v ola , v olb output voltage at low state v vdd = 12 v, i out = 10 ma 5.5 mv v oapda , v oapdb driver output (v outa , v outb ) active pull down v vdda and v vddb unpowered, i outa , i outb = 200 ma 1.75 2.1 v
10 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) parameters that has only typical values, are not production tested and guaranteed by design. 7.10 switching characteristics v vcci = 3.3 v or 5.5 v, 0.1- f capacitor from vcci to gnd, v vdda = v vddb = 12 v, 1- f capacitor from vdda and vddb to vssa and vssb, load capacitance c out = 0 pf, t j = ? 40 c to +125 c, unless otherwise noted (1) . parameter test conditions min typ max unit t rise output rise time, see figure 28 c vdd = 10 f, c out = 1.8 nf, v vdda , v vddb = 12 v, f = 1 khz 5 16 ns t fall output fall time, see figure 28 c vdd = 10 f, c out = 1.8 nf , v vdda , v vddb = 12 v, f = 1 khz 6 12 ns t pwmin minimum input pulse width that passes to output, see figure 25 and figure 26 output does not change the state if input signal less than t pwmin 10 20 ns t pdhl propagation delay at falling edge, see figure 27 inx high threshold, v inh , to 10% of the output 28 40 ns t pdlh propagation delay at rising edge, see figure 27 inx low threshold, v inl , to 90% of the output 28 40 ns t pwd pulse width distortion in each channel, see figure 27 |t pdlha ? t pdhla |, |t pdlhb ? t pdhlb | 5.5 ns t dm propagation delays matching, |t pdlha ? t pdlhb |, |t pdhla ? t pdhlb |, see figure 27 f = 1 mhz 5 ns t vcci+ to out vcci power-up delay time: uvlo rise to outa, outb, see figure 30 ina or inb tied to vcci 40 s t vdd+ to out vdda, vddb power-up delay time: uvlo rise to outa, outb see figure 31 ina or inb tied to vcci 22 |cm h | high-level common-mode transient immunity (see cmti testing ) slew rate of gnd vs. vssa/b, ina and inb both are tied to gnd or vcci; v cm =1000 v; 100 v/ns |cm l | low-level common-mode transient immunity (see cmti testing ) slew rate of gnd vs. vssa/b, ina and inb both are tied to gnd or vcci; v cm =1000 v; 100 7.11 thermal derating curves current in each channel with both channels running simultaneously figure 1. thermal derating curve for lim iting current per vde figure 2. thermal derating curve for limiting power per vde ambient temperature (c) safety limiting current per channel (ma) 0 50 100 150 200 0 20 40 60 80 100 d001 i vdda/b for vdd=12v i vdda/b for vdd=18v ambient temperature (c) safety limiting power (mw) 0 50 100 150 200 0 400 800 1200 1600 2000 d001
11 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7.12 typical characteristics vdda = vddb = 12 v, vcci = 3.3 v or 5.0 v, t a = 25 c, c l =0pf unless otherwise noted. no load ina = inb = gnd figure 3. vcci quiescent current figure 4. vcci operating current - i vcci figure 5. vcci operating current vs. frequency no load ina = inb = gnd figure 6. vdd per channel quiescent current (i vdda , i vddb ) no load figure 7. vdd per channel operating current - i vdda/b ) no load ina and inb both switching figure 8. per channel operating current (i vdda/b ) vs. frequency temperature (c) vcci operating current (ma) -40 -20 0 20 40 60 80 100 120 140 2.4 2.44 2.48 2.52 2.56 2.6 2.64 2.68 d001 vcci = 3.3v, f s =50khz vcci = 3.3v, f s =1.0mhz vcci = 5.0v, f s =50khz vcci = 5.0v, f s =1.0mhz temperature (c) current (ma) -40 -20 0 20 40 60 80 100 120 140 0.8 1 1.2 1.4 1.6 d001 vdd = 12v vdd = 18v temperature (c) current (ma) -40 -20 0 20 40 60 80 100 120 140 1.2 1.3 1.4 1.5 1.6 d001 vcci = 3.3v vcci = 5.0v frequency (khz) vdd operating current (ma) 0 100 200 300 400 500 600 700 800 900 1000 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 d001 vdd = 12v vdd = 15v frequency (khz) vcci operating current (ma) 0 100 200 300 400 500 600 700 800 900 1000 2.5 2.52 2.54 2.56 2.58 2.6 d001 vcci = 3.3v vcci = 5.0v temperature (c) vdd operating current (ma) -40 -20 0 20 40 60 80 100 120 140 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 d001 vdd = 12v, f s =50khz vdd = 12v, f s =1.0mhz vdd = 15v, f s =50khz vdd = 15v, f s =1.0mhz
12 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb = 12 v, vcci = 3.3 v or 5.0 v, t a = 25 c, c l =0pf unless otherwise noted. figure 9. vcci uvlo threshold voltage figure 10. vcci uvlo threshold hysteresis voltage figure 11. 8v vdd uvlo threshold voltage figure 12. 8v vdd uvlo threshold hysteresis figure 13. 5v vdd uvlo threshold voltage figure 14. 5v vdd uvlo threshold hysteresis temperature ( q c) uvlo thresholds (v) -40 -20 0 20 40 60 80 100 120 140 5 5.2 5.4 5.6 5.8 6 d001uvlo v vdd_on v vdd_off temperature (c) uvlo hysteresis (mv) -40 -20 0 20 40 60 80 100 120 140 188 192 196 200 204 208 212 d001 temperature (c) uvlo thresholds (v) -40 -20 0 20 40 60 80 100 120 140 2.4 2.5 2.6 2.7 2.8 2.9 d001 v vcci_on v vcci_off temperature (c) uvlo hysteresis (mv) -40 -20 0 20 40 60 80 100 120 140 500 510 520 530 540 d001 temperature (c) uvlo thresholds (v) -40 -20 0 20 40 60 80 100 120 140 7.5 7.8 8.1 8.4 8.7 9 d001 v vdd_on v vdd_off temperature ( q c) uvlo hysteresis (mv) -40 -20 0 20 40 60 80 100 120 140 320 330 340 350 360 d001uvlo
13 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb = 12 v, vcci = 3.3 v or 5.0 v, t a = 25 c, c l =0pf unless otherwise noted. figure 15. ina/inb/dis high and low threshold voltage figure 16. ina/inb/dis high and low threshold hysteresis figure 17. out pullup and pulldown resistance figure 18. propagation delay, rising and falling edge figure 19. propagation delay matching, rising and falling edge t pdlh ? t pdhl figure 20. pulse width distortion temperature (c) in/dis threshold hysteresis (mv) -40 -20 0 20 40 60 80 100 120 140 750 775 800 825 850 875 d001 temperature (c) pulse width distortion (ns) -40 -20 0 20 40 60 80 100 120 140 -3 -2 -1 0 1 2 3 d001 temperature (c) propagation delay matching (ns) -40 -20 0 20 40 60 80 100 120 140 -2 -1 0 1 2 3 d001 rising edge falling edge temperature (c) propagation delay (ns) -40 -20 0 20 40 60 80 100 120 140 20 22.5 25 27.5 30 32.5 35 37.5 d001 rising edge (t pdlh ) falling edge (t pdhl ) temperature (c) 5hvlvwdqfh -40 -20 0 20 40 60 80 100 120 140 0 2 4 6 8 10 d001 output pull-up output pull-down temperature (c) in/dis thresholds (v) -40 -20 0 20 40 60 80 100 120 140 0.5 1 1.5 2 2.5 d001 in/dis high in/dis low
14 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb = 12 v, vcci = 3.3 v or 5.0 v, t a = 25 c, c l =0pf unless otherwise noted. c l = 1.8 nf figure 21. rise time and fall time figure 22. disable response time figure 23. output active pulldown voltage figure 24. minimum pulse that changes output temperature (c) output active pull down voltage (v) -40 -20 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 d001 vdd open vdd = 0v temperature (c) minimum input pulse (ns) -40 -20 0 20 40 60 80 100 120 140 4 5 6 7 8 9 10 d001 temperature (c) rising and falling time (ns) -40 -20 0 20 40 60 80 100 120 140 0 2 4 6 8 10 d001 rising falling temperature (c) dis response time (ns) -40 -20 0 20 40 60 80 100 120 140 32 36 40 44 48 52 56 60 d001 dis low to high dis high to low
15 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 parameter measurement information 8.1 minimum pulses a typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. to change the output stage on outa or outb, one has to assert longer pulses than t pw(min) , typically 10 ns, to guarantee an output state change. see figure 25 and figure 26 for detailed information of the operation of deglitch filter. figure 25. deglitch filter ? turn on figure 26. deglitch filter ? turn off 8.2 propagation delay and pulse width distortion figure 27 shows how one calculates pulse width distortion (t pwd ) and delay matching (t dm ) from the propagation delays of channels a and b. it can be measured by ensuring that both inputs are in phase. figure 27. delay matching and pulse width distortion 8.3 rising and falling time figure 28 shows the criteria for measuring rising (t rise ) and falling (t fall ) times. for more information on how short rising and falling times are achieved see output stage figure 28. rising and falling time criteria 20% t rise 80% 90% 10% t fall inx outx t pwm < t pwmin v inh v inl inx outx t pwm < t pwmin v inl v inh ina/b t pdlha outa outb t pdlhb t dm t pdhlb t pdhla t pwdb = |t pdlhb t t pdhlb |
16 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.4 input and disable response time figure 29 shows the response time of the disable function. for more information, see disable pin . figure 29. disable pin timing 8.5 power-up uvlo delay to output before the driver is ready to deliver a proper output state, there is a power-up delay from the uvlo rising edge to output and it is defined as t vcci+ to out for vcci uvlo, which is 40 s typically, and t vdd+ to out for vdd uvlo, which is 22 s typically. it is recommended to consider proper margin before launching pwm signal after the driver vcci and vdd bias supply is ready. figure 30 and figure 31 show the power-up uvlo delay timing diagram for vcci and vdd. if ina or inb are active before vcci or vdd have crossed above their respective on thresholds, the output will not update until t vcci+ to out or t vdd+ to out after vcci or vdd crossing its uvlo rising threshold. however, when either vcci or vdd receive a voltage less than their respective off thresholds, there is < 1 s delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. this asymmetric delay is designed to ensure safe operation during vcci or vdd brownouts. figure 30. vcci power-up uvlo delay figure 31. vdda/b power-up uvlo delay ina/b dis outa t pdhl 10% 10% dis low response time t pdlh dis high response time 90% 90% 10% v dish v disl v inl v inh vcci, inx vddx v vdd_on outx t vdd+ to out v vdd_off vcci, inx vddx v vcci_on outx v vcci_off t vcci+ to out
17 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.6 cmti testing figure 32 is a simplified diagram of the cmti testing configuration. figure 32. simplified cmti testing setup 10 9 11 vddb outb vssb 15 14 16 vdda outa vssa functional isolation isolation barrier input logic 2 1 8 5 3 4 vcci dis gnd vcci inb ina copyright ? 2017, texas instruments incorporated outb outa vss common mode surge generator gnd vdd vcc vcc
18 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9 detailed description 9.1 overview in order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. there are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. this is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-v logic signal capable of only delivering a few ma. the UCC21220 , UCC21220a are flexible dual gate driver s which can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors. UCC21220 and UCC21220a have many features that allow it to integrate well with control circuitry and protect the gates it drives such as: disable pin, and under voltage lock out (uvlo) for both input and output voltages. the UCC21220 , UCC21220a also hold its outputs low when the inputs are left open or when the input pulse is not wide enough. the driver inputs are cmos and ttl compatible for interfacing with digital and analog power controllers alike. each channel is controlled by its respective input pins (ina and inb), allowing full and independent control of each of the outputs. 9.2 functional block diagram 10 9 11 driver vddb outb vssb 12 13 nc nc uvlo demod mod 15 14 16 driver vdda outa vssa uvlo demod mod functional isolation isolation barrier 2 1 3,8 4 6 7 gnd inb nc nc ina vcci copyright ? 2017, texas instruments incorporated 200 k : 200 k : uvlo vcci deglitch filter deglitch filter 5 dis 50 k :
19 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9.3 feature description 9.3.1 vdd, vcci, and under voltage lock out (uvlo) the UCC21220 and UCC21220a have an internal under voltage lock out (uvlo) protection feature on the supply circuit blocks between the vdd and vss pins for both outputs. when the vdd bias voltage is lower than v vdd_on at device start-up or lower than v vdd_off after start-up, the vdd uvlo feature holds the effected output low, regardless of the status of the input pins (ina and inb). when the output stages of the driver are in an unbiased or uvlo condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (illustrated in figure 33 ). in this condition, the upper pmos is resistively held off by r hi-z while the lower nmos gate is tied to the driver output through r clamp . in this configuration, the output is effectively clamped to the threshold voltage of the lower nmos device, typically around 1.5v, when no bias power is available. figure 33. simplified representation of active pull down feature the vdd uvlo protection has a hysteresis feature (v vdd_hys ). this hysteresis prevents chatter when there is ground noise from the power supply. also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly. the input side of the UCC21220 and UCC21220a also have an internal under voltage lock out (uvlo) protection feature. the device isn't active unless the voltage, vcci, is going to exceed v vcci_on on start up. and a signal will cease to be delivered when that pin receives a voltage less than v vcci_off . and, just like the uvlo for vdd, there is hystersis (v vcci_hys ) to ensure stable operation. table 1. vcci uvlo feature logic condition inputs outputs ina inb outa outb vcci-gnd < v vcci_on during device start up h l l l vcci-gnd < v vcci_on during device start up l h l l vcci-gnd < v vcci_on during device start up h h l l vcci-gnd < v vcci_on during device start up l l l l vcci-gnd < v vcci_off after device start up h l l l vcci-gnd < v vcci_off after device start up l h l l vcci-gnd < v vcci_off after device start up h h l l vcci-gnd < v vcci_off after device start up l l l l r hi_z vdd r clamp out vss r clamp is activated during uvlo output control
20 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table 2. vdd uvlo feature logic condition inputs outputs ina inb outa outb vdd-vss < v vdd_on during device start up h l l l vdd-vss < v vdd_on during device start up l h l l vdd-vss < v vdd_on during device start up h h l l vdd-vss < v vdd_on during device start up l l l l vdd-vss < v vdd_off after device start up h l l l vdd-vss < v vdd_off after device start up l h l l vdd-vss < v vdd_off after device start up h h l l vdd-vss < v vdd_off after device start up l l l l (1) " x " means l, h or left open. 9.3.2 input and output logic table assume vcci, vdda, vddb are powered up (see vdd, vcci, and under voltage lock out (uvlo) for more information on uvlo operation modes), table 3 shows the operation with ina, inb and dis and the corresponding output state. table 3. input/output logic table (1) inputs dis outputs note ina inb outa outb l l l or left open l l disables both driver outputs if asserted high, enables if set low or left open. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. bypass using a 1nf low esr/esl capacitor close to dis pin when connecting to a c with distance. l h l or left open l h h l l or left open h l h h l or left open h h left open left open l or left open l l it is recommended to tie ina/inb to ground if not used to achieve better noise immunity. x x h l l - 9.3.3 input stage the input pins (ina, inb, and dis) of UCC21220 and UCC21220a are based on a ttl and cmos compatible input-threshold logic that is totally isolated from the vdd supply voltage. the input pins are easy to drive with logic-level control signals (such as those from 3.3-v micro-controllers), since the UCC21220 and UCC21220a have a typical high threshold (v inah ) of 1.8 v and a typical low threshold of 1 v, which vary little with temperature (see figure 12 and figure 16 ). a wide hysterisis (v ina_hys ) of 0.8 v makes for good noise immunity and stable operation. if any of the inputs are ever left open, internal pull-down resistors force the pin low. these resistors are typically 200 k for ina/b and 50 k for dis (see functional block diagram ). however, it is still recommended to ground an input if it is not being used. since the input side of UCC21220 or UCC21220a are isolated from the output drivers, the input signal amplitude can be larger or smaller than vdd, provided that it doesn ? t exceed the recommended limit. this allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient vdd for their mosfet/igbt gate. that said, the amplitude of any signal applied to ina or inb must never be at a voltage higher than vcci.
21 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9.3.4 output stage the UCC21220 and UCC21220a output stages feature a pull-up structure which delivers the highest peak- source current when it is most needed, during the miller plateau region of the power-switch turn on transition (when the power switch drain or collector voltage experiences dv/dt). the output stage pull-up structure features a p-channel mosfet and an additional pull-up n-channel mosfet in parallel. the function of the n-channel mosfet is to provide a boost in the peak-sourcing current, enabling fast turn on. this is accomplished by briefly turning on the n-channel mosfet during a narrow instant when the output is changing states from low to high. the on-resistance of this n-channel mosfet (r nmos ) is approximately 1.47 when activated. the r oh parameter is a dc measurement and it is representative of the on-resistance of the p-channel device only. this is because the pull-up n-channel device is held in the off state in dc condition and is turned on only for a brief instant when the output is changing states from low to high. therefore the effective resistance of the UCC21220 and UCC21220a pull-up stage during this brief turn-on phase is much lower than what is represented by the r oh parameter. the pull-down structure of the UCC21220 and UCC21220a are composed of an n-channel mosfet. the r ol parameter, which is also a dc measurement, is representative of the impedance of the pull-down state in the device. both outputs of the UCC21220 and UCC21220a are capable of delivering 4-a peak source and 6-a peak sink current pulses. the output voltage swings between vdd and vss provides rail-to-rail operation, thanks to the mos-out stage which delivers very low drop-out. figure 34. output stage vdd out vss pull up shoot- through prevention circuitry input signal r oh r ol r nmos
22 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9.3.5 diode structure in UCC21220 and UCC21220a figure 35 illustrates the multiple diodes involved in the esd protection components. this provides a pictorial representation of the absolute maximum rating for the device. figure 35. esd structure 9.4 device functional modes 9.4.1 disable pin setting the dis pin high shuts down both outputs simultaneously. pull the dis pin low (or left open) allows UCC21220 and UCC21220a to operate normally. the dis pin is quite responsive, as far as propagation delay and other switching parameters are concerned (see figure 22 ). the dis pin is only functional (and necessary) when vcci stays above the uvlo threshold. it is recommended to tie this pin to gnd if the dis pin is not used to achieve better noise immunity. 1 2 5 ina inb dis 6 v 6 v 4 gnd 3,8 vcci 20 v 15 14 20 v 11 10 vddb outb outa vssa 9 16 vssb vdda
23 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the UCC21220 and UCC21220a effectively combine both isolation and buffer-drive functions. the flexible, universal capability of the UCC21220 (with up to 5.5-v vcci and 18-v vdda/vddb) allows the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for mosfets, igbts or gan transistor. with integrated components, advanced protection features (uvlo and disable) and optimized switching performance; the UCC21220 and UCC21220a enable designers to build smaller, more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market. 10.2 typical application the circuit in figure 36 shows a reference design with UCC21220 or UCC21220a driving a typical half-bridge configuration which could be used in several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. figure 36. typical application schematic 10 9 11 vddb outb vssb 15 14 16 vdda outa vssa functional isolation isolation barrier input logic 2 1 8 5 3 4 copyright ? 2017, texas instruments incorporated c boot c vdd vss r off r on r gs r off r on c in vdd r boot vdd hv dc-link sw vcci dis gnd vcci inb ina r dis p c c vcc c in r in dis vcc vcc pwm-a pwm-b i/o r gs c dis
24 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical application (continued) 10.2.1 design requirements table 4 lists reference design parameters for the example application: UCC21220 or UCC21220a driving 650-v mosfets in a high side-low side configuration. table 4. UCC21220 and UCC21220a design requirements parameter value units power transistor ipp65r150cfd - vcc 5.0 v vdd 12 v input signal amplitude 3.3 v switching frequency (f s ) 100 khz dc link voltage 400 v 10.2.2 detailed design procedure 10.2.2.1 designing ina/inb input filter it is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the signal at the output. however, a small input r in -c in filter can be used to filter out the ringing introduced by non-ideal layout or long pcb traces. such a filter should use an r in in the range of 0 to100 and a c in between 10 pf and 100 pf. in the example, an r in = 51 and a c in = 33 pf are selected, with a corner frequency of approximately 100 mhz. when selecting these components, it is important to pay attention to the trade-off between good noise immunity and propagation delay. 10.2.2.2 select external bootstrap diode and its series resistor the bootstrap capacitor is charged by vdd through an external bootstrap diode every cycle when the low side transistor turns on. charging the capacitor involves high-peak currents, and therefore transient power dissipation in the bootstrap diode may be significant. conduction loss also depends on the diode ? s forward voltage drop. both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit. when selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes or sic schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss introduced by reverse recovery and related grounding noise bouncing. in the example, the dc-link voltage is 400 v dc . the voltage rating of the bootstrap diode should be higher than the dc-link voltage with a good margin. therefore, a 600-v ultrafast diode, mura160t3g, is chosen in this example. a bootstrap resistor, r boot , is used to reduce the inrush current in d boot and limit the ramp up slew rate of voltage of vdda-vssa during each switching cycle, especially when the vssa(sw) pin has an excessive negative transient voltage. the recommended value for r boot is between 1 and 20 depending on the diode used. in the example, a current limiting resistor of 2.2 is selected to limit the inrush current of bootstrap diode. the estimated worst case peak current through d boot is, where ? v bdf is the estimated bootstrap diode forward voltage drop around 4 a. (1) | : dd bdf dboot pk boot v v 12v 1.5v i 4a r 2.7
25 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10.2.2.3 gate driver output resistor the external gate driver resistors, r on /r off , are used to: 1. limit ringing caused by parasitic inductances/capacitances. 2. limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery. 3. fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss. 4. reduce electromagnetic interference (emi). as mentioned in output stage , the UCC21220 and UCC21220a have a pull-up structure with a p-channel mosfet and an additional pull-up n-channel mosfet in parallel. the combined peak source current is 4 a. therefore, the peak source current can be predicted with: (2) where ? r on : external turn-on resistance. ? r gfet_int : power transistor internal gate resistance, found in the power transistor datasheet. ? i o+ = peak source current ? the minimum value between 4 a, the gate driver peak source current, and the calculated value based on the gate drive loop resistance. (3) in this example: (4) (5) therefore, the high-side and low-side peak source current is 2.3 a and 2.5 a respectively. similarly, the peak sink current can be calculated with: (6) where ? r off : external turn-off resistance, r off =0 in this example; ? v gdf : the anti-parallel diode forward voltage drop which is in series with r off . the diode in this example is an mss1p4. ? i o- : peak sink current ? the minimum value between 6 a, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance. (7) dd bdf oa nmos oh on gfet _ int || v v i min 4a, r r r r ? ? ? 1 dd bdf gdf oa ol off on gfet _ int || v v v i min 6a, r r r r ? ? ? 1 dd ob nmos oh on gfet _ int v 12v i 2.5a r r r r 1.47 || 5 2.2 1. | 5 | | : : : : dd bdf oa nmos oh on gfet _ int v v 12v 0.8v i 2.3a r r r r 1.47 || 5 2.2 1.5 || | : : : : dd ob nmos oh on gfet _ int v i min 4a, r r r r || ? ? ? 1 dd gdf ob ol off on gfet _ int v v i min 6a, r r r r || ? ? ? 1
26 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated in this example, (8) (9) therefore, the high-side and low-side peak sink current is 5.0 a and 5.4a respectively. importantly, the estimated peak current is also influenced by pcb layout and load capacitance. parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. therefore, it is strongly recommended that the gate driver loop should be minimized. on the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (c iss ) of the power transistor is very small (typically less than 1 nf), because the rising and falling time is too small and close to the parasitic ringing period. 10.2.2.4 estimating gate driver power loss the total loss, p g , in the gate driver subsystem includes the power losses of the UCC21220 and UCC21220a (p gd ) and the power losses in the peripheral circuitry, such as the external gate drive resistor. bootstrap diode loss is not included in p g and not discussed in this section. p gd is the key power loss which determines the thermal safety-related limits of the UCC21220 and UCC21220a, and it can be estimated by calculating losses from several components. the first component is the static power loss, p gdq , which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. p gdq is measured on the bench with no load connected to outa and outb at a given vcci, vdda/vddb, switching frequency and ambient temperature. figure 5 and figure 8 shows the operating current consumption vs. operating frequency with no load. in this example, v vcci = 5 v and v vdd = 12 v. the current on each power supply, with ina/inb switching from 0 v to 3.3 v at 100 khz is measured to be i vcci 2.5 ma, and i vdda = i vddb 1.5 ma. therefore, the p gdq can be calculated with (10) the second component is switching operation loss, p gdo , with a given load capacitance which the driver charges and discharges the load during each switching cycle. total dynamic loss due to load switching, p gsw , can be estimated with where ? q g is the gate charge of the power transistor. (11) if a split rail is used to turn on and turn off, then vdd is going to be equal to difference between the positive rail to the negative rail. so, for this example application: (12) u u u gsw p 2 12v 100nc 100khz 240mw u u u gsw dd g sw p 2 v q f u u u gdq vcci vcci vdda dda vddb ddb p v i v i v i 50m w dd bdf gdf oa ol off on gfet _ int v v v 12v 0.8v 0.85v i 5.0a r r r r 0.55 0 5 || 1. | : : : dd gdf ob ol off on gfet _ int v v 12v 0.85v i 5.4a r r r r 0.55 0 1 | .5 | | : : :
27 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated q g represents the total gate charge of the power transistor switching 480 v at 14 a provided by the datasheet, and is subject to change with different testing conditions. the UCC21220 and UCC21220a gate driver loss on the output stage, p gdo , is part of p gsw . p gdo will be equal to p gsw if the external gate driver resistances are zero, and all the gate driver loss is dissipated inside the UCC21220 and UCC21220a. if there are external turn- on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances. importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 a/6 a, however, it will be non-linear if the source/sink current is saturated. therefore, p gdo is different in these two scenarios. case 1 - linear pull-up/down resistor: (13) in this design example, all the predicted source/sink currents are less than 4 a/6 a, therefore, the UCC21220 and UCC21220a gate driver loss can be estimated with: (14) case 2 - nonlinear pull-up/down resistor: where ? v outa/b (t) is the gate driver outa and outb pin voltage during the turn on and off transient, and it can be simplified that a constant current source (4 a at turn-on and 6 a at turn-off) is charging/discharging a load capacitor. then, the v outa/b (t) waveform will be linear and the t r_sys and t f_sys can be easily predicted. (15) for some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the p gdo will be a combination of case 1 and case 2, and the equations can be easily identified for the pull-up and pull- down based on the above discussion. therefore, total gate driver loss dissipated in the gate driver UCC21220 and UCC21220a, p gd , is: (16) which is equal to 127 mw in the design example. 10.2.2.5 estimating junction temperature the junction temperature (t j ) of the UCC21220 and UCC21220a can be estimated with: where ? t c is the UCC21220 and UCC21220a case-top temperature measured with a thermocouple or some other instrument, jt is the junction-to-top characterization parameter from the thermal information table. importantly, jt is developed based on jedec standard pcb board and it is subject to change when the pcb board layout is different. for more information, please visit application report - semiconductor and ic package thermal metrics . (17) using the junction-to-top characterization parameter ( jt ) instead of the junction-to-case thermal resistance (r jc ) can greatly improve the accuracy of the junction temperature estimation. the majority of the thermal energy of most ics is released into the pcb through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). r jc can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an ic package. in all other cases, use of r jc will inaccurately gdo 240mw 5 || 1.47 0.55 p 60mw 2 5 || 1.47 2.2 1.5 0.55 0 1.5 : : : u | ? : : : : : : : ? 1 gsw oh nmos ol gdo oh nmos on gfet _ int ol off on gfet _ int p r r r p 2 r r r r r r || || || r r u ? ? ? 1 gd gdq gdo p p p a o ? ? u u u u ? ? ? ? ? ? 3 3 r _ sys f _ sys t t gdo sw dd outa /b outa /b 0 0 p 2 f 4a v v t dt 6a v t dt j c jt gd t t p < u
28 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated estimate the true junction temperature. jt is experimentally derived by assuming that the amount of energy leaving through the top of the ic will be similar in both the testing environment and the application environment. as long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees celsius. for more information, see the layout guidelines and semiconductor and ic package thermal metrics application report . 10.2.2.6 selecting vcci, vdda/b capacitor bypass capacitors for vcci, vdda, and vddb are essential for achieving reliable performance. it is recommended that one choose low esr and low esl surface-mount multi-layer ceramic capacitors (mlcc) with sufficient voltage ratings, temperature coefficients and capacitance tolerances. importantly, dc bias on an mlcc will impact the actual capacitance value. for example, a 25-v, 1- f x7r capacitor is measured to be only 500 nf when a dc bias of 15 v dc is applied. 10.2.2.6.1 selecting a vcci capacitor a bypass capacitor connected to vcci supports the transient current needed for the primary logic and the total current consumption, which is only a few ma. therefore, a 25-v mlcc with over 100 nf is recommended for this application. if the bias power supply output is a relatively long distance from the vcci pin, a tantalum or electrolytic capacitor, with a value over 1 f, should be placed in parallel with the mlcc. 10.2.2.6.2 selecting a vdda (bootstrap) capacitor a vdda capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6 a, and needs to maintain a stable gate drive voltage for the power transistor. the total charge needed per switching cycle can be estimated with where ? q g : gate charge of the power transistor. ? i vdd : the channel self-current consumption with no load at 100khz. ? (18) therefore, the absolute minimum c boot requirement is: where ? v vdda is the voltage ripple at vdda, which is 0.5 v in this example. (19) in practice, the value of c boot is greater than the calculated value. this allows for the capacitance shift caused by the dc bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. therefore, it is recommended to include a safety-related margin in the c boot value and place it as close to the vdd and vss pins as possible. a 50-v 1- f capacitor is chosen in this example. (20) to further lower the ac impedance for a wide frequency range, it is recommended to have bypass capacitor with a low capacitance value, in this example a 100 nf, in parallel with c boot to optimize the transient performance. note too large c boot is not good. c boot may not be charged within the first few cycles and v boot could stay below uvlo. as a result, the high-side fet does not follow input signal command. also during initial c boot charging cycles, the bootstrap diode has highest reverse recovery current and losses. vdd total g sw i @100khz no load 1.5ma q q 100nc 115nc f 100khz boot c =1 f ' total boot vdda q 115nc c 230nf v 0.5v
29 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10.2.2.6.3 select a vddb capacitor chanel b has the same current requirements as channel a, therefore, a vddb capacitor (shown as c vdd in figure 36 ) is needed. in this example with a bootstrap configuration, the vddb capacitor will also supply current for vdda through the bootstrap diode. a 50-v, 10- f mlcc and a 50-v, 220-nf mlcc are chosen for c vdd . if the bias power supply output is a relatively long distance from the vddb pin, a tantalum or electrolytic capacitor with a value over 10 f, should be used in parallel with c vdd . 10.2.2.7 application circuits with output stage negative bias when parasitic inductances are introduced by non-ideal pcb layout and long package leads (e.g. to-220 and to-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. if the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. below are a few examples of implementing negative gate drive bias. figure 37 shows the first example with negative bias turn-off on the channel-a driver using a zener diode on the isolated power supply output stage. the negative bias is set by the zener diode voltage. if the isolated power supply, v a , is equal to 17 v, the turn-off voltage will be ? 5.1 v and turn-on voltage will be 17 v ? 5.1 v 12 v. the channel-b driver circuit is the same as channel-a, therefore, this configuration needs two power supplies for a half-bridge configuration, and there will be steady state power consumption from r z . figure 37. negative bias with zener diode on iso-bias power supply output 10 9 11 vddb outb vssb 15 14 16 vdda outa vssa functional isolation isolation barrier input logic 2 1 8 5 3 4 copyright ? 2017, texas instruments incorporated c a1 r off r on c in hv dc-link sw c a2 + v a r z v z
30 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated figure 38 shows another example which uses two supplies (or single-input-double-output power supply). power supply v a+ determines the positive drive output voltage and v a ? determines the negative turn-off voltage. the configuration for channel b is the same as channel a. this solution requires more power supplies than the first example, however, it provides more flexibility when setting the positive and negative rail voltages. figure 38. negative bias with two iso-bias power supplies 10 9 11 vddb outb vssb 15 14 16 vdda outa vssa functional isolation isolation barrier input logic 2 1 8 5 3 4 copyright ? 2017, texas instruments incorporated c a1 r off r on c in hv dc-link sw c a2 + v a+ + v a-
31 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated the last example, shown in figure 39 , is a single power supply configuration and generates negative bias through a zener diode in the gate drive loop. the benefit of this solution is that it only uses one power supply and the bootstrap power supply can be used for the high side drive. this design requires the least cost and design effort among the three solutions. however, this solution has limitations: 1. the negative gate drive bias is not only determined by the zener diode, but also by the duty cycle, which means the negative bias voltage will change when the duty cycle changes. therefore, converters with a fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this solution. 2. the high side vdda-vssa must maintain enough voltage to stay in the recommended power supply range, which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to refresh the bootstrap capacitor. therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in the other two example circuits. figure 39. negative bias with single power supply and zener diode in gate drive path 10 9 11 vddb outb vssb 15 14 16 vdda outa vssa functional isolation isolation barrier input logic 2 1 8 5 3 4 copyright ? 2017, texas instruments incorporated c boot c vdd vss c z v z r off r on r gs c z v z r off r on r gs c in vdd r boot vdd hv dc-link sw
32 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10.2.3 application curves figure 40 and figure 41 shows the bench test waveforms for the design example shown in figure 36 under these conditions: vcc = 5.0 v, vdd = 12 v, f sw = 100 khz, v dc-link = 400 v. channel 1 (yellow): ina pin signal. channel 2 (blue): inb pin signal. channel 3 (pink): gate-source signal on the high side power transistor. channel 4 (green): gate-source signal on the low side power transistor. in figure 40 , ina and inb are sent complimentary 3.3-v, 20%/80% duty-cycle signals with 200ns deadtime. the gate drive signals on the power transistor have a 200-ns dead time with 400v high voltage on the dc-link, shown in the measurement section of figure 40 . note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement. figure 41 shows a zoomed-in version of the waveform of figure 40 , with measurements for propagation delay and deadtime. importantly, the output waveform is measured between the power transistors ? gate and source pins, and is not measured directly from the driver's outa and outb pins. figure 40. bench test waveform for ina/b and outa/b figure 41. zoomed-in bench-test waveform
33 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 11 power supply recommendations the recommended input supply voltage (vcci) for UCC21220 and UCC21220a is between 3 v and 5.5 v. the output bias supply voltage (vdda/vddb) range from 9.2v to 18v. the lower end of this bias supply range is governed by the internal under voltage lockout (uvlo) protection feature of each device. one mustn ? t let vdd or vcci fall below their respective uvlo thresholds (for more information on uvlo see vdd, vcci, and under voltage lock out (uvlo) ). the upper end of the vdda/vddb range depends on the maximum gate voltage of the power device being driven by UCC21220 and UCC21220a. the UCC21220 and UCC21220a have a recommended maximum vdda/vddb of 18 v. a local bypass capacitor should be placed between the vdd and vss pins. this capacitor should be positioned as close to the device as possible. a low esr, ceramic surface mount capacitor is recommended. it is further suggested that one place two such capacitors: one with a value of 10- f for device biasing, and an additional 100-nf capacitor in parallel for high frequency filtering.. similarly, a bypass capacitor should also be placed between the vcci and gnd pins. given the small amount of current drawn by the logic circuitry within the input side of UCC21220 and UCC21220a, this bypass capacitor has a minimum recommended value of 100 nf.
34 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 12 layout 12.1 layout guidelines consider these pcb layout guidelines for in order to achieve optimum performance for the UCC21220 and UCC21220a. 12.1.1 component placement considerations ? low-esr and low-esl capacitors must be connected close to the device between the vcci and gnd pins and between the vdd and vss pins to support high peak currents when turning on the external power transistor. ? to avoid large negative transients on the switch node vssa (hs) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized. ? it is recommended to bypass using a 1-nf low esr/esl capacitor, c dis , close to dis pin when connecting to a c with distance 12.1.2 grounding considerations ? it is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. this will decrease the loop inductance and minimize noise on the gate terminals of the transistors. the gate driver must be placed as close as possible to the transistors. ? pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local vssb- referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. the bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the vdd bypass capacitor. this recharging occurs in a short time interval and involves a high peak current. minimizing this loop length and area on the circuit board is important for ensuring reliable operation. 12.1.3 high-voltage considerations ? to ensure isolation performance between the primary and secondary side, one should avoid placing any pcb traces or copper below the driver device. a pcb cutout is recommended in order to prevent contamination that may compromise the UCC21220 and UCC21220a isolation performance. ? for half-bridge, or high-side/low-side configurations, one should try to increase the clearance distance of the pcb layout between the high and low-side pcb traces. 12.1.4 thermal considerations ? a large amount of power may be dissipated by the UCC21220 and UCC21220a if the driving voltage is high, the load is heavy, or the switching frequency is high (refer to estimating gate driver power loss for more details). proper pcb layout can help dissipate heat from the device to the pcb and minimize junction to board thermal impedance ( jb ). ? increasing the pcb copper connecting to vdda, vddb, vssa and vssb pins is recommended, with priority on maximizing the connection to vssa and vssb (see figure 43 and figure 44 ). however, high voltage pcb considerations mentioned above must be maintained. ? if there are multiple layers in the system, it is also recommended to connect the vdda, vddb, vssa and vssb pins to internal ground or power planes through multiple vias of adequate size. ensure that no traces or coppers from different high-voltage planes overlap.
35 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 12.2 layout example figure 42 shows a 2-layer pcb layout example with the signals and key components labeled. figure 42. layout example figure 43 and figure 44 shows top and bottom layer traces and copper. note there are no pcb traces or copper between the primary and secondary side, which ensures isolation performance. pcb traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node vssa (sw), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. figure 43. top layer traces and copper figure 44. bottom layer traces and copper pwm input (top layer) vcci caps. (top layer) gnd plane (bot. layer) input filters (top layer) pcb cutout bootstrap diode (bot. layer) to high side transistor to low side transistor vdd caps. (bot. layer) bootstrap caps (bot. layer)
36 UCC21220 , UCC21220a slusck0c ? november 2017 ? revised august 2018 www.ti.com product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated layout example (continued) figure 45 and figure 46 are 3d layout pictures with top view and bottom views. note the location of the pcb cutout between the primary side and secondary sides, which ensures isolation performance. figure 45. 3-d pcb top view figure 46. 3-d pcb bottom view
37 UCC21220 , UCC21220a www.ti.com slusck0c ? november 2017 ? revised august 2018 product folder links: UCC21220 UCC21220a submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 13 device and documentation support 13.1 documentation support 13.1.1 related documentation for related documentation see the following: ? isolation glossary 13.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 5. related links parts product folder sample & buy technical documents tools & software support & community UCC21220 click here click here click here click here click here UCC21220a click here click here click here click here click here 13.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 13.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 13.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 19-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pUCC21220ad active soic d 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 p21220a UCC21220ad preview soic d 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 21220a UCC21220adr preview soic d 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 21220a UCC21220d active soic d 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 21220 UCC21220dr active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 21220 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 19-sep-2018 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant UCC21220dr soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 package materials information www.ti.com 24-aug-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) UCC21220dr soic d 16 2500 367.0 367.0 38.0 package materials information www.ti.com 24-aug-2018 pack materials-page 2

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